This invention relates generally to integrated circuits and in particular to a programmable memory address decode array with vertical transistors.
Technological advances have permitted semiconductor integrated circuits to comprise significantly more circuit elements in a given silicon area. Reducing and eliminating defects in the circuit elements has, however, become increasingly more difficult with the increased number of circuit elements. To achieve higher population capacities, circuit designers strive to reduce the size of the individual circuit elements to maximize available die real estate. The reduced size makes these circuit elements increasingly susceptible to defects caused by material impurities during fabrication.
Nevertheless, defects are identifiable upon completion of the integrated circuit fabrication by testing procedures, either at the semiconductor chip level or after complete packaging. Scrapping or discarding defective integrated circuits when defects are identified is economically undesirable, particularly if only a small number of circuit elements are actually defective.
Relying on zero defects in the fabrication of integrated circuits is an unrealistic option. Therefore, redundant circuit elements are provided on integrated circuits to reduce the number of scrapped integrated circuits. If a primary circuit element is determined to be defective, a redundant circuit element is substituted for the defective primary circuit element. Substantial reductions in scrap are achieved by using redundant circuit elements without substantially increasing the cost of the integrated circuit.
One type of integrated circuit device using redundant circuit elements is integrated memory circuits, such as dynamic random access memories (DRAMs), static random access memories (SRAMs), video random access memories (VRAMs), and erasable programmable read only memories (EPROMs). Typical integrated memory circuits comprise millions of equivalent memory cells arranged in arrays of addressable rows and columns. The rows and columns of a memory cell array are the primary circuit elements of the integrated memory circuit. By providing redundant circuit elements, either as rows or columns, defective primary rows or columns can be replaced with functional ones.
Decoders perform an essential task by selecting the functional rows and columns of the integrated memory array. The memory cells within an integrated memory array are coupled to an electronic system through the address and data lines. Decoder circuits interface between the address lines and the array of memory cells.
A conventional decoder circuit of a semiconductor memory device comprises one or more separate decoder units which supply decode output signals according to an input address signal. A row decoder selects the appropriate row and the column decoder selects the appropriate column corresponding to a particular memory cell within the memory array. The pair of decoder output signals are also referred to wordlines, which corresponds to a row decoder, and bitlines, which correspond to a column decoder.
Decoders contain the required logic functions required to properly address desired memory cells within a memory cell array. Traditionally, decoder circuits are masked with a logic configuration for selecting rows and columns. Once the logic function has been masked, it is very difficult to make a correction. An improperly programmed decoder results in an integrated memory device functioning incorrectly.
A technique used to correct a decoder after it has been masked is to use ion beams or lasers. Making corrections to a decoder after it has been programmed is a very time consuming and cumbersome process using these common techniques.
To provide some level of programmability in a decoder, antifuses are used. To program an antifuse xe2x80x9con,xe2x80x9d a large programming voltage is applied across the antifuse terminals, breaking down the interposed dielectric and forming a conductive link between the antifuse terminals. An unprogrammed xe2x80x9coffxe2x80x9d state, in which the antifuse is fabricated, presents a high resistance between the antifuse terminals. The antifuse can be reprogrammed to an xe2x80x9conxe2x80x9d state in which a low resistance connection between the antifuse terminals is desired, but only for a very limited number of times.
Therefore, a problem with current row and column decoders is that once they are programmed with a particular logic function, changes are often difficult and complex to make. If a decoder is not properly programmed, the integrated memory circuit will likewise not function properly, which defeats the purpose of having redundant circuit elements on an integrated memory array. There are elaborate techniques to reprogram a decoder, but these techniques are cumbersome and time consuming. Therefore, there is a need in the art for a decoder that can be easily reprogrammed.
Another problem with decoders is that as integrated circuit technology advances, the size of individual circuit elements decreases. Designers can include more storage cells in a memory array on a semiconductor substrate. As the number of storage cells increases, the number of components in a decoder likewise need to increase.
Increasing the storage capacity of a decoder array requires a reduction in the size of the transistors and other components in order to increase the decoder""s density. However, memory density is typically limited by a minimum lithographic feature size (F) imposed by lithographic processes used during fabrication. For example, the present generation of high density decoders require an area of 8F2 per bit of data. Therefore, there is a need in the art to provide even higher density decoders in order to further support the increased storage capacity of integrated memory circuits.
A programmable memory address decode array with vertical transistors is implemented for selecting only functional lines in a memory array. The decoder is programmed at memory test and is easily reprogrammed.
In one embodiment, a decoder for a semiconductor memory comprises a number of address input lines, a number of output lines, and an array of logic cells connected between the address input and the output to select an output line responsive to address bits received via the address input. Each logic cell includes at least a pair of transistors formed on opposing sides of a common pillar of semiconductor material that extends outwardly from a working surface of a substrate to form source, drain and body regions for the transistors. A number of floating gates are also formed wherein each gate is associated with a side of the pillar and a number of control lines are also formed wherein each control line is associated with a floating gate.
In particular, a decoder for a semiconductor memory comprises an array of logic cells. Each logic cell includes at least a pair of transistors formed on opposing sides of a common pillar of semiconductor material that forms source, drain and body regions for the transistors. At least a pair of floating gates are disposed adjacent to the opposing sides of the pillar. At least one first source and drain interconnection line, interconnecting one of the first source and drain regions of one of the logic cells is formed. A plurality of output lines, each output line interconnecting one of the second source and drain regions of one of the memory cells is also formed. A plurality of address input lines for receiving address bits are formed, wherein the array of logic cells connected between the plurality of address input lines and the plurality of output lines selects an output line responsive to the received address bits.
In another illustrative embodiment, a memory device comprises an array of memory cells, each memory cell includes a transistor, a capacitor, and a bit contact. Addressing circuitry is coupled to the array of memory cells via wordlines for accessing individual memory cells in the array of memory cells. The addressing circuitry includes a row decoder having a number of address input lines, a number of output lines, and an array of logic cells connected between the address input and the output to select a wordline responsive to address bits received via the address input. A read circuit is coupled to the array of memory cells via bitlines for reading individual memory cells in the array of memory cells. The read circuit includes a column decoder having a number of address input lines, a number of output lines, and an array of logic cells connected between the address input and the output to select a bitline responsive to address bits received via the address input.
In another embodiment, a computer system comprises a memory device. The memory device includes an array of memory cells, each memory cell includes a transistor, a capacitor, and a bit contact. Addressing circuitry is coupled to the array of memory cells via wordlines for accessing individual memory cells in the array of memory cells. The addressing circuitry includes a row decoder having an address input having N input lines, an output having 2N output lines, and an array of logic cells connected between the address input lines and the output lines to select a wordline responsive to address bits received via the address input lines. A read circuit is coupled to the array of memory cells via bitlines for reading individual memory cells in the array of memory cells. The read circuit includes a column decoder having an address input having N input lines, an output having 2N output lines, and an array of logic cells connected between the address input and the output to select a bitline responsive to address bits received via the address input.
In yet another embodiment, a method of forming a logic array for a decoder is provided. The method includes several steps as described below. A plurality of first conductivity type semiconductor pillars are formed upon a substrate, each pillar having top and side surfaces. Next, a plurality of first source and drain regions are formed, of a second conductivity type, each of the first source and drain regions formed proximally to an interface between the pillar and the substrate. Forming a plurality of second source and drain regions, of a second conductivity type, each of the second source and drain regions formed within one of the pillars and distal to the substrate and separate from the first and source drain region. Forming a gate dielectric on at least a portion of the side surface of the pillars. A plurality of floating gates is formed, each of the floating gates formed substantially adjacent to a portion of the side surface of one of the pillars and separated therefrom by the gate dielectric. A plurality of control lines are formed, each of the control lines formed substantially adjacent to one of the floating gates and insulated therefrom, such that there are two control lines between the common pillars. Forming an intergate dielectric, interposed between ones of the floating gates and one of the control lines. Forming an intergate dielectric, interposed between the two control lines between the common pillars. Forming a plurality of address input lines that interconnect the control lines. At least one first source/drain interconnection line interconnecting ones of the first source/drain regions is formed and a plurality of data lines are formed, each data line interconnecting ones of the second/source drain regions.
In a still further embodiment, a method of forming a decoder logic array on a substrate is provided. The method comprises the steps of forming a first source/drain layer at a surface of the substrate. Then a semiconductor epitaxial layer on the first source/drain layer is formed. Next, a second source/drain layer at a surface of the epitaxial layer is formed. Etching is performed, in a first direction, for a plurality of substantially parallel first troughs in the epitaxial layer. The steps continue with forming an insulator in the first troughs, etching, in a second direction that is substantially orthogonal to the first direction, a plurality of substantially parallel second troughs in the epitaxial layer, forming a gate dielectric layer substantially adjacent to sidewall regions of the second troughs, and forming a conductive layer in the second troughs. A portion of the conductive layer is removed in the second troughs such that floating gate regions are formed along the sidewall regions therein and separated from the sidewall regions by the gate dielectric layer. Finally, the steps include forming an intergate dielectric layer on exposed portions of the floating gate regions in the second troughs, and forming control line regions and address input lines between opposing floating gate regions in the second troughs and separated from the floating gate regions in the second troughs by the intergate dielectric layer.
In another embodiment, a method of forming a decoder logic array on a substrate is provided, comprising the steps of forming a first source/drain layer at a surface of the substrate, forming a semiconductor epitaxial layer on the first source/drain layer, forming a second source/drain layer at a surface of the epitaxial layer, etching, in a first direction, a plurality of substantially parallel first troughs in the epitaxial layer. The steps also include forming an insulator in the first troughs, etching, in a second direction that is substantially orthogonal to the first direction, a plurality of substantially parallel second troughs in the epitaxial layer, forming a gate dielectric layer substantially adjacent to sidewall regions of the second troughs, forming a conductive layer in the second troughs and removing a portion of the conductive layer in the second troughs such that floating gate regions are formed along the sidewall regions therein and separated from the sidewall regions by the gate dielectric layer. Finally, the following steps are performed. Forming an intergate dielectric layer on exposed portions of the floating gate regions in the second troughs, forming split control line regions and address input lines between opposing floating gate regions in the second troughs, separating from the floating gate regions in the second troughs by the intergate dielectric layer, and separating the split control lines by the intergate dielectric layer.
Therefore, bulk semiconductor and semiconductor-on-insulator embodiments of the present invention provide a high density programmable memory address decode device. If a floating gate of transistor data is used to represent a logic function, an area of only 2F2 is needed, where F is the minimum lithographic feature size. The programmability of the decoder device is particularly advantageous for selecting functional lines in a memory array without having to program a logic array with a mask. If a logic change needs to be made to the decoder, selected transistors in the logic array are simply reprogrammed.
A programmable memory decode device thus allows a user to define a selected output line in response to address bits received via an address input. The logic function is defined without having to actually mask a logic array. In different embodiments of the invention, bulk semiconductor, semiconductor-on-insulator, single control lines, split control lines and floating gates of varying scope are described. Still other and further embodiments, aspects and advantages of the invention will become apparent by reference to the drawings and by reading the following detailed description.